1. Field of the Invention
The present invention relates to integrated circuits and processes for their manufacture and, in particular, to integrated circuits that include dual thickness cobalt silicide layers and methods for their manufacture.
2. Description of the Related Art
In Metal-Oxide-Semiconductor (MOS) device manufacturing, self-aligned metal silicide layers (also known as "salicide" layers) are useful in reducing the sheet resistance of polysilicon interconnections, source regions and drains regions, as well as contact resistance. See, for example, Stanley Wolf, Silicon Processing for the VLSI Era, Vol. I, 388-399 (Lattice Press, 1986).
FIGS. 1-3 illustrate a conventional process for forming a metal silicide layer over a polysilicon gate, a source region and a drain region of an MOS transistor structure within an integrated circuit (IC).
A conventional MOS transistor structure 10 includes a thin gate oxide layer 12 overlying P-type silicon substrate 14 between N-type drain region 16 and N-type source region 18, both of which are formed in P-type silicon substrate 14. A conventional MOS transistor structure 10 also includes a polysilicon gate 20 overlying thin gate oxide layer 12, as well as field oxide regions 22, which isolate MOS transistor structure 10 from neighboring semiconductor device structures (not shown). Gate sidewall spacers 24, typically formed of silicon dioxide or silicon nitride, are disposed on the lateral edges of polysilicon gate 20 and thin gate oxide layer 12.
In a conventional metal silicide formation process, a metal layer 28 is deposited over the surface of MOS transistor structure 10, as illustrated in FIG. 2. Metal layer 28 is ordinarily deposited by a multi-directional evaporative or sputtering-based physical vapor deposition (PVD) process or a multi-directional chemical vapor deposition (CVD) process and is, therefore, of essentially uniform thickness over the entire surface of MOS transistor structure 10.
Wherever metal layer 28 is in contact with silicon surfaces (i.e. source region 18, drain region 16 and the polysilicon surface of polysilicon gate 20) the metal is reacted to form a metal silicide layer. The reaction conditions, such as temperature and gaseous ambient, employed for the metal silicide layer formation are selected to foster the reaction of the metal layer with silicon surfaces while impeding reaction of the metal layer with silicon dioxide or silicon nitride surfaces (i.e. the gate sidewall spacers and field oxide regions).
A selective etch is then used to remove unreacted metal from the surface of the gate sidewall spacers and field oxide regions, as well as any unreacted metal residue still remaining above the source region, drain region and polysilicon gate. The etch is "selective" since it does not remove the metal silicide layer that was formed on the surface of the silicon and polysilicon regions. The result, illustrated in FIG. 3, is a metal silicide layer 32 on the surface of drain region 16, a metal silicide layer 34 on the surface of source region 18 and a metal silicide layer 36 on the surface of polysilicon gate 20.
The use of cobalt silicide layers is becoming increasingly common in semiconductor devices. During cobalt silicide layer formation it is often beneficial to utilize a bilayer system, which includes an initially deposited cobalt layer covered with a "capping" layer of titanium, titanium-tungsten (TiW), or titanium-nitride (TiN), prior to the reaction of the cobalt with silicon surfaces to form cobalt silicide layers. The use of capping layers is reported to improve device electrical parameters, to reduce cobalt overgrowth of oxide regions and, in the case of titanium capping layers, to provide a gettering mechanism that prevents cobalt oxidation during the silicide formation process. See, for example, Berti et al., U.S. Pat. No. 5,736,461; A. C. Berti and V. Bolkhovsky, A Manufacturable Process for the Formation of Self Aligned Cobalt Silicide in a Sub Micrometer CMOS Technology, VMIC Conference, June 9-10, 267-273 (1992); and K. Maex and R. Schreutelkamp, Self-Aligned Silicides for ULSI, Mat. Res. Soc. Symp. Proc., Vol. 260, 133-144 (1992), all of which are hereby incorporated by reference.
Conventional cobalt silicide processes can result in the formation of cobalt silicide layers on the source region, drain region and polysilicon gate regions of each MOS transistor structure within an IC that are all of essentially the same thickness. Since silicide layer thickness is, however, a critical factor in semiconductor device performance, it is often desirable to form cobalt silicide layers of different thicknesses on predetermined regions of a given semiconductor device or on predetermined semiconductor devices within a given IC in a controllable manner. For example, two separate semiconductor devices with different source and drain junction depths may be present in a single IC. In such a situation, the semiconductor devices with shallow source and drain junction depths may require a relatively thin cobalt silicide layer on those regions, in order to reduce the risk of junction spiking, while the semiconductor devices with deep junction depths still require a relatively thick cobalt silicide layer on those regions so as to reduce contact resistance.
U.S. Pat. No. 4,877,755 to Rodder describes a lengthy and complex dual thickness silicide process. This process relies on two separately applied silicide barrier layers that are intended to sequentially block metal silicide layer formation on the gate polysilicon and source and drain regions. Such a process is undesirable from the standpoint of both cost and processing time since it requires two metal silicide formation steps as well as two silicide barrier layer deposition steps. Furthermore, this process does not allow formation of silicide layers with varied thickness on individual areas within an IC, and thus only yields one essentially uniform thickness silicide on all polysilicon gates and another essentially uniform thickness silicide on all source and drain regions within an IC.
U.S. Pat. No. 5,034,348 to Hartswick et al. describes a dual thickness silicide process, which includes a step of applying a refractory metal layer (such as titanium) over the gate polysilicon layer prior to gate polysilicon patterning. In this process, following gate polysilicon patterning, the refractory metal layer is reacted with the gate polysilicon to form a first metal silicide layer on the gate polysilicon. A second metal silicide layer is subsequently formed over the source and drain regions. In addition to requiring two metal silicide formation steps, this process suffers from other limitations that render it unsuitable for use in conventional MOS processing. For example, the process makes it difficult to dope the polysilicon gate underneath the first metal silicide layer during conventional source and drain region formation processes, as well as to pattern the refractory metal/polysilicon multilayer gate structure to deep submicron dimensions. Furthermore, this process does not allow formation of silicide layers with varied thickness on individual areas within an IC, and thus only yields one essentially uniform thickness silicide on all polysilicon gates and another essentially uniform thickness silicide on all source and drain regions within an IC.
Still needed in the field is a process for the controlled formation of dual thickness cobalt silicide layers on an IC that requires a minimum number of steps, is compatible with standard MOS processing, and provides for the controlled formation of cobalt silicide layers of different thicknesses on individual predetermined polysilicon gates and/or source and drain regions within an IC. Also needed is an IC structure that includes cobalt silicide layers of varied thicknesses on predetermined polysilicon gates and/or source and drain regions.